1. Field of the Invention
The present invention relates to an improvement in yield in a manufacture of a semiconductor device and more specifically, relates to a structure of a semiconductor substrate and a method of manufacturing the semiconductor substrate for reducing an influence of a heavy metal element.
2. Description of the Prior Art
[Prior Art 1]
A semiconductor is classified into a P type and an N type depending on an impurity contained in the semiconductor. A semiconductor device functions in accordance with a combination of the P type and the N type. The impurity to be contained in the semiconductor is typically introduced by an ion implantation and a diffusion method. It is technically difficult for these methods to form a steep gradient of an impurity concentration and to form a layer of lower impurity concentration on the layer of higher impurity concentration. In order to solve this problem, used is a semiconductor substrate (hereinafter referred to as an "epitaxial substrate") on which an epitaxial growth is performed on a main front surface. By the use of this method, it is possible to easily form the steep gradient of the impurity concentration and form the layer of lower impurity concentration on the layer of higher impurity concentration. A high pressure resistance of a semiconductor element, an improvement in a latch-up resistance, the improvement in an a ray strength or the like can be thus expected. The epitaxial substrate is also used for the reason why the epitaxial substrate has less crystal imperfections on the substrate surface.
[Prior Art 2]
On the other hand, a high integration and a fine formation of the semiconductor device cause a process of manufacturing the semiconductor device to be complicated. Thus, the manufacturing process is often influenced by a metal contamination during the process. Since a metal causes a deterioration of device properties such as a precipitation in a silicon crystal, a reduction of the metal contamination is attempted. However, due to a technical problem and a cost problem, it is disadvantageously difficult to completely prevent this metal contamination.
A metal contaminant invading the semiconductor substrate is captured on a portion other than a device active region on the main front surface side of the semiconductor substrate, whereby a gettering technique can prevent the deterioration of device properties even if the metal contamination occurs. Since the gettering technique is performed at relatively low cost and also improves a yield, it is widely used for a manufacture of the semiconductor device. One method of this gettering technique is an extrinsic gettering method for forming a gettering site by a polysilicon for capturing a metallic element on a rear surface of the semiconductor substrate.
The importance of the above-described prior arts 1 and 2 has been recently rising in the manufacture of the semiconductor device. The prior arts have been frequently used. Thus, the semiconductor substrate is sometimes used by the combination of the prior arts 1 and 2. Referring to FIGS. 1A-1I, the method of manufacturing the semiconductor substrate by the combination of the prior arts 1 and 2 will be described below as the prior art. FIGS. 1A-1I show, in order of processes, the processes of manufacturing the semiconductor substrate of the prior art.
In the first place, as shown in FIG. 1A, a Si single-crystal ingot containing a highly concentrated impurity is cylindrically worked by means of an outer diameter grinding. This cylindrical ingot 1 is cut into blocks. The cut ingot 1 is then sliced, whereby a Si substrate 2 is cut out in wafer shape (FIG. 1B). FIGS. 1C-1I showing the subsequent processes show a cross section of the Si substrate 2. The cut-out Si substrate 2 (FIG. 1C) is chamfered in order to bevel peripheral corners (FIG. 1D). The Si substrate 2 is then mechanically polished in order to smooth the Si substrate 2 and to improve parallelism (FIG. 1E). Next, a damaged layer (not shown) formed on a front surface layer of the Si substrate 2 is removed by etching. A polysilicon layer 4 to be the gettering site is then formed up to about 500-2000 nm on the rear surface or both of the front and rear surfaces of the Si substrate 2 (FIG. 1F). A blocking oxide film 5 for preventing an auto-doping is subsequently formed on the polysilicon layer 4 (FIG. 1G). Next, a mechanical chemical polishing is performed so as to thereby remove the polysilicon layer 4 and the blocking oxide film 5 on the main front surface side of the Si substrate 2 and to mirror polish the main front surface of the removed Si substrate 2 (FIG. 1H). An epitaxial Si layer 6 is finally grown to about 0.1-25 .mu.m on the front surface of this polished Si substrate 2 (FIG. 1I).
The above-mentioned manufacturing process can manufacture the semiconductor substrate having the epitaxial Si layer 6 on the main front surface of the semiconductor substrate 2 and the polysilicon layer 4 to be the gettering site on the rear surface thereof.
On the other hand, the process of manufacturing the epitaxial substrate typically includes the process of removing a natural oxide film on the Si substrate and of performing the epitaxial growth. In this process, it is necessary to heat the Si substrate to 1000-1200.degree. C. Even during the process of manufacturing the semiconductor device, it is also necessary to perform a thermal oxidation process and a heat treatment of a drive-in or the like of a well. The heat treatment is frequently performed at about 700-1200.degree. C.
Due to such a heat treatment, the impurity such as boron, phosphorus, antimony and arsenic, which the Si substrate 2 is highly doped with, is flied out from the Si substrate 2. That is, a so-called outward diffusion phenomenon occurs. As a result, many dopant impurities enter the polysilicon layer 4 to be the gettering site. A grain of the polysilicon layer 4 is greatly grown. In the polysilicon, a strain field in a grain boundary and the strain field due to a lattice mismatching are one of the gettering site. Thus, it is known that an increase of grain size causes a considerable reduction of gettering capability (see p.p. 194-199, "VLSI process control engineering", Hideki Tsuya, Maruzen Corp.).
As described above, in case of manufacturing the semiconductor substrate by the combination of the prior arts 1 and 2 or in case of manufacturing the semiconductor device using such a semiconductor substrate, the grain size in a gettering layer is increased due to the outward diffusion phenomenon of the dopant impurity by a high-temperature heat treatment. This causes a problem in which the gettering capability is reduced.